The present invention relates to an insulated gate type semiconductor device comprising micronized, insulated gate type transistors, and also to a method of manufacturing the same.
Remarkable advantages have been made in the field of micronization of the elements of MOS integrated circuits. Efforts have been made to reduce the channel length of a MOS transistor in order to raise the switching speed of the transistor. The reduction of the channel length, however, causes the following problems which affect the characteristics of the transistor.
The first problem is the shorter the channel length, the lower the threshold voltage in the channel region, due to so-called "short-channel effect." More specifically, the threshold voltage of the transistor sharply falls to a value within the channel region as understood from FIG. 1 showing the relation between the gate channel length (Lch) and threshold voltage (Vth). In other words, voltage Vth greatly changes in the short-channel region as channel length Lch slightly varies. This is because the gate voltage required to electronically invert the channel-region surface will fall since the gap between the source and drain regions of the transistor becomes short as channel length Lch slightly reduces, and the influence of the depletion layer formed near the source and drain regions increases drastically. Generally, the substrate forming the channel region has a potential equal or very similar to that of the source region. Therefore, the electric field stretching between the source and drain regions is strong at that part of the channel region surface which is close to the drain region. As a result, the fall of threshold voltage most prominently affects the characteristic of this part of the channel region surface.
The second problems is: the shorter the channel length Lch, the more intense the electric field generated by the voltage applied between the source region and the and drain region. Hence, the probability for the channel current to cause impact ionization increases. The electrons or holes generated by the impact ionization have a high energy, and some of the electrons or holes are injected into the gate insulator and farther into the gate electrode, whereby a gate current is generated. Part of this current is trapped within the gate insulator. As a result, the operation characteristics of the transistor (e.g., the threshold voltage or the channel conductance) vary, deteriorating the reliability of the transistor. Impact ionization occurs mainly in that portion of the channel region which is close to the drain region since the electric field stretching between the source and drain regions is intense in said portion of the channel region. Therefore, MOS transistors of LDD (Lightly Doped Drain) structure have been developed in which, as shown in FIG. 8, that portion of the drain region which is located close to the channel region has a lower impurity concentration than the other portions, thereby to suppress impact ionization. More specifically, the MOS transistor of LDD structure comprises P-type semiconductor substrate 10 and patterned field insulation film 11 formed on substrate 10. An opening of film 11 exposes a portion of substrate 10. In this portion of substrate 10, or an element region, N-type regions 12 and 13 forming a source region are formed. Also in the element region, N-type regions 14 and 15, which form the drain region, are formed, separated from regions 12 and 13. Regions 12 and 14 are N.sup.+ regions having a high impurity concentration of about 10.sup.20 cm.sup.-3, and regions 13 and 15 are N.sup.- regions having a relatively low impurity concentration of about 10.sup.18 cm.sup.-3. On the part (or gate insulation film 16) of insulation film 11 which is located on the portion of substrate 10 which extends between the source and drain regions, gate electrode 17 is formed. Interlayer insulation film 18 is formed on the upper surface of the unfinished product. Two contact holes are cut in films 16 and 18, exposing source region 12 and drain region 14. Aluminium interconnection layers 19 and 20 are formed on insulation film 18, filling up the contact holes. Interconnection layers 19 and 20 therefore are electrically connected to source region 12 and drain region 14, respectively.
Since drain region 15 contacting the channel region has a low impurity concentration, it can absorb part of the voltage applied between the source and drain, thus weakening the electric field concentrated in that portion of the channel region continuous to the drain region. The transistor can therefore be sufficiently reliable in spite of the reduction of channel length Lch.
However, the MOS transistor of FIG. 2 has a drawback. Since source region 13 and drain region 15, both contacting the channel region, have relatively low impurity concentrations, their resistances are equivalently high. The transistor inevitably have a low operation speed. When a number of MOS transistors of this type are coupled in series, forming a device, the operation speed of this device will be considerably low.
FIG. 3 is a cross-sectional view of a 2-input NAND circuit comprising two enhancement N-channel MOS transistors 41 and 42 and one depletion N-channel MOS transistor 43 used as a load element. Transistors 41 and 42 have the same structure shown in FIG. 2. As shown in FIG. 3, the NAND circuit comprises a P semiconductor substrate 51. The source region of transistor 42 is made of N.sup.+ diffusion region 52a and N.sup.- diffusion region 52b both formed in the surface of substrate 51. The drain region of transistor 52 is made of N.sup.+ diffusion region 53a and N.sup.- diffusion region 53b both formed in the surface of substrate 51. Gate electrode 54 of transistor 42 is provided above that portion of substrate 51 which is located between N.sup.+ regions 52b and 53b. The source region of MOS transistor 41 is formed of N.sup.+ diffusion region 55a and N.sup.- diffusion region 55b both formed in the surface of substrate 51. The drain region of MOS transistor 41 is made of N.sup.+ diffusion region 56a and N.sup.- diffusion region 56b both formed in the surface of substrate 51. Gate electrode 57 of transistor 41 is provided above that portion of substrate 51 which is located between N.sup.+ regions 55b and 56b. MOS transistor 43 comprises N diffusion region 58 used as the source region, N diffusion region 59 used as the drain region, and gate electrode 61 provided above that portion of substrate 51 which is located between N regions 58 and 59. N region 59 is connected to high-voltage power source V.sub.DD, and N region 52a is connected to low-potential power source V.sub.SS. Input signals A1 and A2 are supplied to gate electrodes 54 and 57. N regions 53a and 55a are electrically connected to each other. Gate electrode 61, N region 58 and N region 56a are also electrically connected. The node of electrode 61, N region 58 and N region 56a functions as the output terminal of the NAND circuit to supply output signal Vout, which is an inverse to the logic product of input signals A1 and A2.
FIG. 4 is an equivalent circuit diagram of the two-input NAND circuit. As shown in this figure, the NAND circuit comprises MOS transistors 43, 41 and 42 coupled in series in this order. Signals A1 and A2 are supplied to the gates of transistors 41 and 42. Output signal Vout is supplied from the node of transistors 41 and 43. The source and drain of MOS transistor 41 and also the source and drain of MOS transistor 42 (all indicated by triangles in FIG. 4) are regions having low impurity concentrations and therefore have high resistances. Input signals A1 and A2 are either voltage V.sub.SS or V.sub.DD, and their logic levels are either "1" or "0". An inverse to the logic product of these signals is output signal Vout. More precisely, voltage V.sub.DD and voltage V.sub.SS are, for example, 5 V and 0 V. Voltage V.sub.DD (5 V) is applied through depletion MOS transistor 43 to the drain region of enhancement MOS transistor 41 whose gate is connected to receive signal A1. MOS transistors 41 and 42 are made conducting or nonconducting in accordance with the logic levels of input signals A1 and A2. When transistors 41 and 42 are turned on, output signal Vout will be voltage of 0 V. When one of these transistors is turned on, while the other transistor is turned off, output signal Vout will be voltage of 5 V. Since MOS transistors 41 and 42 are of the LDD structure, their source and drain regions have high resistances. The resistors equivalent to these resistances are coupled in series between high-potential power source V.sub.DD and low-voltage power source V.sub.SS. These equivalent resistors increase the time constant for lowering the output voltage (Vout) from 5 V to 0 V. The operation speed of the NAND circuit is inevitably reduced very much. The reduction of this speed is proportional to the number of MOS transistors connected between power sources V.sub.DD and V.sub.SS. This problem is inherent not only in a circuit including a depletion MOS transistor used as a load element, but also in a CMOS circuit including P-channel MOS transistors coupled to high-potential power source V.sub.DD.